Introduction to ASK modulation
In this post, we are going to understand the fundamental of Digital Modulation from the basic. An example of VHDL implementation of a digital modulator is given at the end of the post.

Digital Modulation technique is very important in the telecommunication world and substituted the analog modulation since is more flexible and can be implemented if a small and cheap electronics. We will focus on the implementation of the digital modulator.
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Figure 1 – Example of digital modulator Architecture

The basic implementation of Amplitude-shift keying (ASK) is a form of amplitude modulation that represents digital data as variations in the amplitude of a carrier wave.

For example, the transmission of the binary symbol ‘1’ can be represented by transmitting a fixed-amplitude carrier wave and fixed frequency for a bit duration of T seconds (bit rate). If the signal value is ‘1’ then the carrier signal will be transmitted; otherwise, a signal value of ‘0’ will be transmitted.

Like AM, an ASK is also linear and very sensitive to atmospheric noise, distortions, propagation conditions so the efficiency in terms of Signal-to-Noise ratio is very low. The ASK modulation and demodulation processes are relatively inexpensive. The ASK technique is also commonly used to transmit digital data over optical fiber.

More general, ASK can be used to transmit a finite number of amplitudes, each assigned a unique pattern of binary digits. Usually, each amplitude encodes an equal number of bits.
For example, if we decide to encode 2 bit per symbol transmitted, the amplitude transmitted are:

00 => A0

01 => A1

10 => A2

11 => A3

Of course, increasing the number of different transmitted amplitude (the number of bit we transmit for each symbol), the Signal-to-noise ratio must increase.

ASK modulator architecture
A typical architecture of a modulator is reported in Figure 1
From the left:

· Digital source

· Bit-formatter

· Mapper

· Low-pass interpolator shaping filter

· Optional Up-converter

The digital source can be either internal or external and provides the serial bit-stream to be transmitted at bit rate Rb. The serial bit-stream is “packetized” into a meta-symbol of two or more bit, two bits in this example. The output frequency of the meta-symbols is Rb/Np, where Np is the number of bit of the meta-symbol. The meta symbols are mapped following the desired modulation scheme.

For ASK example, the input symbol is mapped in an N-BIT discrete amplitude.

In this post, we will focus on the mapper using 2 bit for the input meta-symbol and 8 bit for mapper output.

VHDL implementation of ASK mapper
The mapper can receive a 2-bit input i.e. four different meta symbols value:

· 00

· 01

· 10

· 11

The meta-symbol will be mapped into an 8-bit amplitude. The mapping scheme can be decided to maximize the channel efficiency. In this example, we will map the 4 values into 4 different equally distributed intervals. For 8 bit mapping, the possible values are 0, 1, .. 255. Dividing the interval 0..255 in 4 we get 256/4 = 64

· 00 => 63

· 01=> 127

· 10 => 191

· 11 => 255

A possible VHDL code implementation is given below:

1. library ieee;

2. use ieee.std_logic_1164.all;

3. use ieee.numeric_std.all;

4.

5. entity mapper_ask is

6. port (

7. i_clk : in std_logic;

8. i_rstb : in std_logic;

9. i_meta_sym : in std_logic_vector(1 downto 0);

10. o_mapper : out std_logic_vector(7 downto 0));

11. end mapper_ask;

12.

13. architecture rtl of mapper_ask is

14. type t_mapper_table is array(0 to 3) of integer range 0 to 255;

15. constant mapper_table : t_mapper_table := (

16. 63,

17. 127,

18. 191,

19. 255);

20.

21. signal r_meta_sym : integer range 0 to 3; -- used as mapper_table pointer

22.

23. begin

24.

25. p_mapper_ask : process(i_clk,i_rstb)

26. begin

27. if(i_rstb='0') then

28. r_meta_sym w_mapper );

50.

51. u_dds_sine : dds_sine

52. port map(

53. i_clk => i_clk ,

54. i_rstb => i_rstb ,

55. i_sync_reset => i_sync_reset ,

56. i_fcw => i_fcw ,

57. i_start_phase => i_start_phase ,

58. o_sine => w_sine );

59.

60. p_modulator_ask_simple : process(i_clk,i_rstb)

61. begin

62. if(i_rstb='0') then

63. r_upconverted '0');

64. r_molulator '0');

65. elsif(rising_edge(i_clk)) then

66. r_upconverted